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HYDRA Video-Audio platform

HYDRA platform

  • Video and Audio processing proprietary architecture
  • Multi-processor architecture including:
  • KM211_KVARC MPU or other vendor’s CPU as a head processor, running OS
  • HYDRA engine, represented by a number of
    • a. Bit-steam processors for efficient real-time data parsing or compressing (BS_CPU)
    • b. DSP processors, floating and fixed point, 4xSuperscalar, 4xSIMD, 4xVector (DC_CPU) put on a high-performance HYDRA bus
  • Scalable from 3 to 32 processor cores per chip
  • Max. DSP Performance of 30 MPUs*600Mhz*4(multiple-operands command-options)=72GFLOPs
  • OS Linux 2.6, if based on KVARC head MPU
  • ARM cores as a head processor compatible
  • Smart-card embedded reader and Crypto-accelerators options
  • Natural performance and power control (by using the needed number of cores)
  • Field of use: set-top-box’s, real-time HD compression in Web cameras with Ethernet connection, other heavy-duty calculations applications