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KVARC 32bit MPU with Android KitKat and Linux

Download KVARC microprocessor core brief

Download page: Software and Toolchains for KVARC MPU
  • 32 bit proprietary microprocessor architecture, Harvard, RISC
  • 32/16 bit instructions, 32 bit operands
  • 5-stage pipeline, static branch predictionКВАРК
  • Optionally: MMU and configurable cache memory block
  • DSP instruction set extension
  • FPU optional module with single and double precision
  • Single stage 16x16 (opt. 32x32) multiplicator
  • Fast interrupt switching of just 5 cycles
  • Low power sleep modes 
  • 1.1 DMIPS/MHz
  • 600MHz clock frequency at 90nm process
  • 0.2 mm2 core area, without cache and MMU memories at 90nm process
  • FreeRTOS and Linux 2.6 ported
  • C-compiler GNU (GCC v 3.4.3 & v 4.6.0), Eclipse based SDK
  • JTAG, GDB debugger

 

  • Extended peripheral blocks list, including multimedia applications support

Implementation Technology/Device Die size & Gate count Note Perfomance
In Silicon  

Micron (Russia) HCMOS8D 180 нм, K5512BP1F (NIIMA Progress)

Cell Area - 0,41 мм2
(33,7 Kgates);
Layout - 0,51 мм2
(40 Kgates)

w/o cache & MMU 150 МГц
In Silicon TSMC CLN90G, 90 нм 0,2 мм2 (72 Kgates) w/o cache & MMU
> 400 МГц
2,2 мм2 (780 Kgates) with cache & MMU 48Кб (32Кб+16Кб)
FPGA Xilinx Virtex 4 2000 slices w/o cache & MMU
60 МГц
Altera Cyclone IV 7150 LEs w/o cache & MMU
60 МГц